1. Field of the Invention
The present invention relates to a serial-to-parallel conversion circuit that regenerates a clock signal at a receiving end on the basis of data and a strobe, to perform decoding.
This application is based on Japanese Patent Application No. 2007-183444, the content of which is incorporated herein by reference.
2. Description of Related Art
IEEE 1355 is a conventional known interface standard for space-based devices. Recently, “SpaceWire” has also been proposed as a next-generation interface standard for space-based devices. SpaceWire is a derivative of IEEE 1355 proposed by the European Space Agency (ESA) as a standard for space applications; it is also known as IEEE 1355.2 (for example, see U.S. Pat. No. 5,341,371).
For terrestrial applications, the IEEE 1394 high-speed serial bus is widely used as an interface suitable for connecting together audio-visual equipment, personal computer peripherals, etc.
In IEEE 1355, IEEE 1355.2, IEEE 1394, and similar standards, a clock at the transmission end is recreated at the receiving end from two signals, “data” and “strobe”, sent from the transmission end; therefore, it is not necessary to synchronize the clocks at the transmission and receiving ends, which makes it possible to construct systems at low cost. In addition, these systems offer advantages because of their variable data transmission rate, such as compatibility with various devices.
FIG. 15 shows an example configuration of a serial-to-parallel conversion circuit used in the above-mentioned standards. In this serial-to-parallel conversion circuit, a clock CLK is generated by taking the exclusive OR of “data D” and “strobe S” received from the transmission end. The clock CLK is then input to multiple stages of flip-flops FF0, FF1, . . . , FFn constituting a shift register 100.
Accordingly, the input data (“Data” in FIG. 16) is latched in the flip-flop FF0, provided at the first stage of the shift register 100, at the rising edge of the clock CLK.
When implementing a conventional serial-to-parallel conversion circuit, such as that shown in FIG. 15, in an actual circuit, a delay occurs until the clock CLK and the input Data are input to the flip-flop FF0. As shown in FIG. 17, there is no problem so long as the clock CLK arrives at the flip-flop FF0 after the input Data changes; however, as shown in FIG. 18, if the clock CLK arrives at the flip-flop FF0 before the input Data changes, the Data level before the change becomes latched in the flip-flop FF0, resulting in a so-called race condition, where the original data to be latched differs from the data actually latched.
One way to eliminate the race condition problem is to input the clock CLK to the flip-flop FF0 via a delay circuit. However, if the serial-to-parallel conversion circuit described above were implemented with general-purpose programmable semiconductor devices, such as CPLDs (Complex PLDs) or FPGAs (Field Programmable Gate Arrays), it would be difficult to provide a delay circuit.
Moreover, when the phase of the clock CLK is delayed by providing a delay circuit, the shortest bit period of the received data is limited by the amount of delay of the clock CLK by the delay circuit. This is a problem because the maximum reception speed is also limited by the amount of delay of the clock CLK.